The crystalline structure of a material is typically classified into one (or more) of three categories, namely single crystalline materials, polycrystalline materials and amorphous materials. Single crystalline materials refer to materials that have a single crystal unit structure, while polycrystalline materials are materials that include a plurality of crystal units. Amorphous materials generally do not have a defined crystal structure as atoms in the amorphous material may be irregularly bonded to each other. Herein a material or layer is referred to as a “non-single crystalline” material or layer if the material or layer is not a single crystalline layer (i.e., it is a polycrystalline and/or amorphous material or layer). Polycrystalline materials typically have a large number of grain boundaries (i.e., the interface between two or more of the plurality of crystal units). These grain boundaries may restrict the movement of carriers such as electrons or holes through polycrystalline materials. To reduce and/or to minimize such reductions in carrier mobility, single crystalline silicon layers are often used, for example, as an active region of a system-on-chip (SOC) device or an active region of a thin film transistor (TFT) having a stacked structure.
A single crystalline silicon layer is one that includes a high density of relatively large single crystal grains. It will be appreciated by those of skill in the art that polycrystalline layers may also have a plurality a single crystal units contained therein, but the size of the grains and the density of large grains is substantially smaller. Generally, a layer is considered to comprise a single crystalline semiconductor layer as opposed to a polycrystalline (or other) layer when the layer contains a high density of single crystal grains that exhibit long-range translational symmetry.
As a single crystalline silicon layer includes a high density of relatively large single crystal grains, it will typically have far fewer grain boundaries than a polycrystalline silicon layer, and hence will exhibit improved carrier mobility. The present inventors have filed a patent application directed to methods of forming single crystalline silicon layers that include a high density of relatively large single crystal grains as Korean Patent Application No. 2004-43265 on Jun. 12, 2004. This patent application was registered as Korean Patent No. 578,787 on May 4, 2006.
According to the methods set forth in the above-identified Korean patent application, a non-single crystalline silicon film such as, for example, an amorphous silicon film is formed on a seed layer that includes single crystalline silicon, and then a laser beam is irradiated onto the amorphous silicon layer so as to change the amorphous silicon layer into the single crystalline silicon layer. The laser beam may be irradiated onto the amorphous silicon layer by, for example, a scanning process. However, when this method is used, sharp protrusions may be formed on the single crystalline silicon layer. FIGS. 1 and 2 are cross-sectional diagrams that illustrate the above-described method of forming a single crystalline silicon layer.
In particular, as shown in FIG. 1, sharp protrusions 112 may be formed on single crystalline silicon layer 100 because the single crystalline silicon layer 100 is formed by a scanning process. As shown in FIG. 2, a laser beam 122 is superimposedly irradiated onto portions II of an amorphous silicon layer 120 in the scanning process so that the protrusions 112 may be formed on the single crystalline silicon layer 100. By “superimposedly irradiated” it is meant that the laser beam melts portions of the layer more than once. When the laser beam 122 is superimposedly irradiated onto the portions II of the amorphous silicon layer 120, the portions II of the amorphous silicon layer 120 are repeatedly melted allowing excessive growth from the seed layer, thereby forming the sharp protrusions 112 from the portions II of the amorphous silicon layer 120. The sharp protrusions 112 may adversely effect the performance of electronic devices grown on or in the single crystalline silicon layer 100.